1. Field of the Invention
The present invention relates to an A/D (analog-digital) converter in which one or more analog voltages to be converted are sampled and held and the sampled and held one or more analog voltages to be converted are compared with a reference voltage given by a voltage change value of a ramp voltage having a voltage value changing monotonically for a certain period or a voltage value proportional to the voltage change value, and each of the one or more analog voltages to be converted is converted to a digital value corresponding to the reference voltage and outputted, and more particularly, to a column-type A/D converter. Particularly, the present invention relates to a ramp voltage generation circuit and a constant current source suitable for the above column-type A/D converter.
2. Description of the Related Art
Recently, high speed and low power consumption are increasingly demanded in an A/D converter used in a solid-state image sensor. In order to satisfy the above demand, a column-type A/D converter is used in many cases (refer to Japanese Unexamined Patent Publication No. 2000-286706).
FIG. 11 is a circuit block diagram showing a schematic constitution of a conventional column-type A/D converter. A column-type A/D converter 51 comprises an inverter circuit 12, a switch RS to short-circuit an input node CPI and an output node CPO of the inverter circuit 12, a capacitor CT to sample an analog voltage to be converted, a ramp voltage generation circuit 50 generating a ramp voltage VRAMP changing its value monotonically for a certain period, a capacitor CR and a switch S3 to transmit the ramp voltage VRAMP to the input node CPI, a counter 15 counting a digital value (n-bit binary signal) according to the voltage value change of the ramp voltage and outputting it, a switch SS to sample the analog voltage to be converted, and a latch circuit 13 to latch a counter output corresponding to the analog voltage to be converted as circuit elements. Furthermore, in FIG. 11, a pixel part 16 of a solid-state image sensor outputting a voltage corresponding to an incident light amount, to the column-type A/D converter 51, and a constant current source Ix to lead the voltage based on the electric charge amount generated by the photoelectric conversion at the pixel part 16, to the node VIN are also illustrated.
The A/D conversion operation of the column-type A/D converter 51 will be described with reference to a timing chart shown in FIG. 12.
At a timing t1, when a switch RX of the pixel part 16 is turned on, a node FD is reset to a voltage VDD, a node VIN is charged to a high potential through a MOS transistor MA. In addition, the switch RS is turned on at the same time, and the input node CPI and the output node CPO of the inverter circuit 12 are short-circuited and the input node CPI is automatically reset to an input determination voltage (auto-zero level) of the inverter circuit 12. Although the switch SS is turned on at the same time, switches S3 and TX are in off state.
At a timing t2, when the switch RX is turned off, a reset voltage appears at the node VIN. At a timing t3, when the switch RS is turned off, a reset voltage is sampled in the capacitor CT.
Then, at a timing t4, when the switch TX is turned on, a photoelectric conversion is performed by a photoelectric conversion element (photodiode) PD and accumulated electric charge is transferred to the node FD, so that the node VIN is shifted to a voltage level (photoelectric conversion level) corresponding to the photoelectric-converted electric charge amount. When the voltage level of the node VIN is stabilized at a timing t5 and the switch TX is turned off and the switch S3 is turned on, a voltage difference between the voltage level (photoelectric conversion level) of the node VIN at that time and an initial voltage of the ramp voltage VRAMP is held in the capacitor CR.
Then, at a timing t6, when the switch SS is turned off, a differential value VSIG between the reset voltage (timing t3) and the photoelectric conversion level (timing 6) of the node VIN is held in the input node CPI as an analog voltage to be converted.
At a timing t7, when a voltage value of the ramp voltage VRAMP starts to increase gradually, the voltage of the input node CPI is also increased so as to be proportional to the voltage increase of the ramp voltage VRAMP. In addition, at the timing t7, the counter 15 starts to count at the same time.
At a timing t8, when the voltage level of the input node CPI exceeds the input determination voltage of the inverter circuit 12, the inverter circuit 12 inverts the output level of the output node CPO. The latch circuit 13 holds the value of the counter output in response to the output change of the output node CPO.
Here, the differential value VSIG corresponds to an incident light amount to the photoelectric conversion element PD, and the value of the latched counter output is equal to an A/D conversion value (digital value) of the differential value VSIG. Thus, when the A/D conversion value held by the latch circuit 13 is outputted, the column-type A/D converter 51 completes the A/D conversion operation of the analog voltage to be converted VSIG.
In addition, a view showing a schematic constitution of the ramp voltage generation circuit 50 is shown in Japanese Unexamined Patent Publication No. 2006-018663.
FIG. 13 is a circuit block diagram showing a schematic constitution of the conventional ramp voltage generation circuit described in the above Japanese Unexamined Patent Publication No. 2006-018663. The conventional ramp voltage generation circuit 50 comprises a stabilization voltage source Vref generating a constant voltage, an operation amplifier AMP1, a MOS transistor MNSF, a resistance Rref to generate a constant current based on an input voltage of the operation amplifier AMP1, MOS transistors MP1 and MP2 and MN1 and MN2 constituting current mirrors, a switch SW_ramp to control a generation timing of a ramp wave, an operation amplifier AMPint, a capacitive load Cint, a stabilization voltage source Vc, and a switch SW_reset to reset a charging amount of the capacitive load Cint.
In addition, in order to avoid complication due to increase of references, the sign allotted to each capacitor (capacitive load) shows the capacitance value of the capacitor as it is, and similarly, the sign allotted to each resistive load shows the resistance value of the resistive load as it is. That is, the same sign of the capacitor is used for the capacitance value and the same sign of the resistance is used for the resistance value of the resistance in the following description.
An output voltage VREF is inputted from the stabilization voltage source to a non-inversion input terminal of the operation amplifier AMP1. Since the non-inversion input terminal and an inversion input terminal of the operation amplifier AMP1 are virtually short-circuited, a voltage VREF—COPY (voltage of node VREF_COPY) inputted to the inversion input terminal is the same as the voltage VREF of the node VREF. Therefore, a current Iref flowing in the resistance Rref is expressed by the following formula 1.
                    Iref        =                                            V              REF                        Rref                    .                                    (        1        )            
Thus, the same current as the current Iref calculated in the formula 1 is led to the transistor MP2 by a current mirror comprising the transistors MP1 and MP2, and the same current Iint as the current Iref is led to the transistor MN2 by a current mirror comprising the transistors MN1 and MN2. That is, the current Iint is calculated by the following formula 2.
                              I          ⁢                                          ⁢          int                =                  Iref          =                                    V              REF                        Rref                                              (        2        )            
The current Iint has a value depending on charging and discharging speed of the charge stored in the capacitive load Cint. When it is assumed that the voltage applied to both ends of the capacitive load Cint is determined by a voltage difference between the inversion input terminal and the output terminal of the operation amplifier AMPint, and the inversion input terminal and the non-inversion input terminal of the operation amplifier is at the same potential due to the virtual short circuit state referring to FIG. 13, the following formula 3 is established.
                                          ⅆ                          (                                                V                  RAMP                                -                Vc                            )                                            ⅆ            t                          =                              I            ⁢                                                  ⁢            int                                C            ⁢                                                  ⁢            int                                              (        3        )            
Here, in the ramp voltage generation circuit 50, when the switch SW_reset is turned on, both ends of the capacitive load Cint becomes the same potential and reset state is provided. In addition, when the switch SW_ramp is turned on, the timing of the current Iint is controlled. That is, the generation timing and the waveform of the ramp voltage are determined by on/off control of both switches.
FIG. 14 shows a waveform example of the ramp voltage generated by the ramp voltage generation circuit 50 and its timing chart. The switch SW_reset is turned on and the capacitor Cint is reset by timing t7. When the reset operation is performed, the voltage VRAMP of the output terminal (output node) of the ramp voltage generation circuit 50 shows the same voltage (Vc) as that of the non-inversion input terminal. Then, when the switch SW_reset is turned off and the switch SW_ramp is turned on at the timing t7, electric charge is drawn from the capacitive load Cint by the constant current Iint, whereby the voltage VRAMP shows a ramp voltage waveform having an inclined angle of θ. This ramp voltage rises from the timing t7 until the switch SW_ramp is turned off after a lapse of time Tint. An increased value (wave crest value) of the ramp voltage VRAMP when the switch SW_ramp is turned off is defined as a full scale voltage VFS.
At this time, the value of the ramp voltage VRAMP at a time “t” from the timing 7 until the lapse of Tint is calculated by the following formula 4 referring to FIG. 14.
                              V          RAMP                =                  Vc          +                                                    V                REF                                                              Rref                  ·                  C                                ⁢                                                                  ⁢                int                                      ·                          (                              t                -                                  t                  ⁢                                                                          ⁢                  7                                            )                                                          (        4        )            
That is, the inclined angle θ of the change of the ramp voltage VRAMP shown in FIG. 14 is expressed by the following formula 5. In addition, the dimension of the inclined angle θ shown in the drawing is (voltage/time) that shows a voltage change per unit time.
                    θ        =                              V            REF                                              Rref              ·              C                        ⁢                                                  ⁢            int                                              (        5        )            
In addition, the full scale voltage VFS shown in FIG. 14 is expressed by the following formula 6 with reference to the above formula 5.
                              V          FS                =                                                            V                REF                                                              Rref                  ·                  C                                ⁢                                                                  ⁢                int                                      ·            T                    ⁢                                          ⁢          int                                    (        6        )            
Meanwhile, according to Razavi, “Design of Analog CMOS Integrated Circuits” McGrawHill 2001, p. 647, p. 650, it is reported that a resistance value of a resistance element or a capacitance value of a capacitive load formed on an integrated circuit is varied by about ±20% among wafers and lots. This fact means that the values of the resistance Rref and the capacitive load Cint have variations of about ±20% in the ramp voltage generation circuit 50. Therefore, when it is assumed that an average value of the resistance Rref and an average value of the capacitive load Cint are Rrefb and Cintb, respectively, the inclined angle θ of the ramp voltage VRAMP takes a range expressed by the following formula 7 based on the formula 5.
                                          V            REF                                              (                              1.2                ·                Rrefb                            )                        ⁢                          (                                                1.2                  ·                  C                                ⁢                                                                  ⁢                int                ⁢                                                                                          ⁢                                                                                        ⁢                b                            )                                      ≤        θ        ≤                              V            REF                                              (                              0.8                ·                Rrefb                            )                        ⁢                          (                                                0.8                  ·                  C                                ⁢                                                                  ⁢                int                ⁢                                                                  ⁢                b                            )                                                          (        7        )            
In addition, since the formula 7 shows a range of the value of the inclined angle θ when the resistance Rref and the capacitive load Cint are most extremely varied, it is known that the variation up to ±30% is generated actually. Thus, the variation of the inclined angle θ causes the variation of about ±30% in full scale voltage.
FIG. 15 is a graph showing the influence of the variation of the inclined angle θ on the A/D conversion result in a case where the A/D converter 51 performs the A/D conversion using the ramp voltage from the ramp voltage generation circuit 50 having a variation in the inclined angle θ. For example, when the inclined angle θ is varied like θ1, θ2 or θ3 in FIG. 15, a time required to reach the auto-zero level differs. According to the example shown in FIG. 15, in the case of the largest inclined angle of θ3, a time required to reach the auto-zero level is the fastest and in the case of the smallest inclined angle of θ1, a time required to reach the auto-zero level is the latest. When the voltage of the node CPI reaches the auto-zero level, the node CPO is inverted and the value of the counter output latched by the latch circuit 13 at that timing is a converted digital value. That is, when the timing of the voltage that reaches the auto-zero level fluctuates, it means that the A/D converted value fluctuates. Therefore, when a digital image is created based on the output value (digital value) from such an A/D converter, the problem is that an image different from a target image (variation in luminance of the image with respect to each chip) is created.